1. Field of the Invention
The present invention relates to a DDC integrable interface cell dedicated to a microprocessor. This invention can be used especially in integrated circuits dedicated to a microprocessor to manage serial communications protocols defined by the DDC standard.
2. Discussion of the Related Art
The DDC standard of the VESA committee defines serial communications protocols. There are several communications protocols, among them DDC1, DDC2B, DDC2AB. The DDC2B and DDC2AB protocols use identical hardware communications means covered by the name I2C. By extension, the term I2C protocol shall be used hereinafter in this document to designate the protocols DDC2B and DDC2AB. The major differences between the DDC1 and I2C protocols are:
the DDC1 protocol clock is represented by a synchronous signal Vsync and the I2C protocol clock is represented by an asynchronous signal SCL, and PA1 the exchange of data elements is unidirectional for the DDC1 protocol and bidirectional for the I2C protocol. PA1 a first data input/output circuit connected to a data bus of the microprocessor, PA1 a second data input/output circuit connected to a communications network working according to at least two different protocols called the DDC1 and I2C protocols, PA1 a data processing circuit between the first data input/output circuit and the second data input/output circuit, and PA1 a control circuit comprising a sequencer, the control circuit being sequenced by the sequencer, the control circuit communicating with a control bus of the microprocessor, the control circuit also communicating with the second data input/output circuit, PA1 wherein said cell comprises a logic circuit to enforce the state of the sequencer as a function of an information element pertaining to the nature of the protocol used.
There already exists an interface cell dedicated to the I2C protocols. This cell which permits transfers according to the DDC2B and DDC2AB protocols is used in applications of communications between a microprocessor, for example that of a microcomputer, and peripherals such as a keyboard, mouse or the like. The I2C protocols permit a transfer between two peripherals by means of a peripheral addressing system from a master to a slave. The DDC2B protocol enables a master to address one of many slaves. The DDC2AB protocol improves the system by proposing the possibility of using a multiple-master mode that authorizes several masters following the same type of exchange.
The DDC standard of the VESA committee has defined the possibility of using a DDC1 protocol simultaneously with a I2C protocol through the use of common means. However, at present, there is no interface cell enabling the simultaneous use of the DDC1 and I2C protocols. The conversion of an already existing I2C cell into a DDC1 cell is not very practical in principle, in view of the scale of the problems raised.